1. Field of the Invention
The present disclosure relates to an organic light emitting diode display device, and more particularly, to an organic light emitting diode display device including a gate driver.
2. Discussion of the Related Art
As an information society progresses, various demands for a display device displaying an image increase. Recently, various flat panel displays (FPDs) such as a liquid crystal display (LCD) device, a plasma display panel (PDP) device, an organic light emitting diode (OLED) display device and a field emission display (FED) device have been utilized.
Among various FPDs, an OLED display device has advantages in response speed, emission efficiency, brightness and viewing angle due to an emissive device. The OLED display device of a current driving type where brightness of a light emitting diode is adjusted by controlling a current has been generally used.
FIG. 1 is a view showing an organic light emitting diode display device according to the related art, and FIG. 2 is a plan view showing a gate driver of an organic light emitting diode display device according to the related art.
In FIG. 1, an organic light emitting diode (OLED) display device according to the related art includes an external system 10, a timing controller 14, a data driver 16, a gate driver 18 and a display panel 12.
The external system 10 supplies an image signal RGB, a vertical synchronization signal Vsync, a horizontal signal Hsync and a clock signal CLK to the timing controller 14. The timing controller 14 outputs a gate control signal GCS for controlling the gate driver 18 and a data control signal DCS for controlling the data driver 16 using the vertical synchronization signal Vsync, the horizontal signal Hsync and the clock signal CLK. In addition, the timing controller 14 rearranges the image signal RGB according to a resolution of the display panel 12 and outputs the rearranged image signal RGB to the data driver 16.
The data driver 16 converts the image signal RGB to an analog pixel signal (a data signal or a data voltage) corresponding to a gray level of the image signal according to the data control signal DCS from the timing controller 14 and supplies the pixel signal to data lines DL1 to DLm of the display panel 12.
The gate driver 18 sequentially supplies a scan signal to gate lines GL1 to GLn according to the gate control signal GCS from the timing controller 14, and thin film transistors (TFTs) of a corresponding horizontal line in the display panel 12 are turned on. The gate driver 18 includes a scan signal generating unit 18a and an emission signal generating unit 18b. The scan signal generating unit 18a supplies the scan signal for determining an addressing time of the data voltage to the gate lines GL1 to GLn, and the emission signal generating unit 18b supplies an emission signal EM for determining an emission time of a pixel P to emission lines EL1 to ELn. The scan signal generating unit 18a and the emission signal generating unit 18b may be formed in the display panel 12 as a gate in panel (GIP) type.
The display panel 12 includes the gate lines GL1 to GLn, the data lines DL1 to DLm and the pixels P at crossing of the gate lines GL1 to GLn and the data lines DL1 to DLm. Lines for supplying a high level voltage Vdd, a low level voltage Vss and a reference voltage Vref, a switching TFT, a driving TFT turned on by the pixel signal through the switching TFT, an emission TFT driven by the emission lines EL1 to ELn and a light emitting diode (LED) are formed in each pixel P.
In the OLED display device according to the related art, the gate driver 18 controls the emission of each pixel P by the scan signal generating unit 18a and the emission signal generating unit 18b. A variation in threshold voltage due to deterioration of the driving TFT may be compensated by making timings of the scan signal and the emission signal different.
For example, the scan signal has a turn-on level and the emission signal has a turn-off level during a period for addressing the data voltage is addressed, the scan signal has a turn-off level and the emission signal has a turn-on level during a period for emitting the pixel P.
Specifically, for sequentially outputting signals by a cascade connection, the emission signal generating unit 18b includes a shift register SR and an inverter INV generating an emission control pulse by inverting the signal from the shift register SR. Similarly, for sequentially outputting signals by a cascade connection, the scan signal generating unit 18a includes a shift register SRG.
However, since the gate driver 18 includes the scan signal generating unit 18a and the emission signal generating unit 18b for generating two signals, control signals for controlling the scan signal generating unit 18a and the emission signal generating unit 18b increase and lines for transmitting the control signals increase.
Further, as shown in FIG. 2, the gate driver 18 of a GIP type is formed in a non-display area of the display panel 12, and an area W for the gate driver 18 which is a sum of a first area W1 for the scan signal generating unit 18a and a second area W2 for the emission signal generating unit 18b increases. Specifically, since the second area W2 for the emission signal generating unit 18b is a sum of an area W2a for the shift register SR and an area W2b for the inverter INV, the area W for the gate driver 18 further increases. As a result, a bezel area, which is a non-display area, of the OLED display device increases due to the gate driver 18 of a GIP type and appearance of the OLED display device is deteriorated.